| Hiring For | Design Verification |
| Job Description | Design Verification |
| Desired Profile | Skills : SV/UVM Test Bentch Development, Any Protocols: (PCI Express or UCIe, CXL or NVM, AXI, ACE or CHI, Ethernet, RoCE or RDMA, DDR or LPDDR or HBM), DV experience in System Verilog/UVM, IP/sub-system and/or SoC level verification based on SV/UVM. Notice Period: Immediate to 30 days |
| Education | BE, Btech ME Mtech, MCA |
| Location | Bangalore, Cochin, Hyderabad , Pune & Chennai |
| career@krazymantra.com |